1. Field of the Invention
The present invention relates to a charge pump type DC-DC converter used in portable electronic devices. More particularly, the invention is directed to suppressing the operation of a parasitic bipolar transistor inherently formed in MOS transistor circuitry used for DC-DC power converters.
2. Description of the Related Art
Decreasing the power consumption rates of portable electronic devices such as cordless phones has been possible in part due to the lower supply voltage requirements of the semiconductor circuitry used in such devices. One type of circuit that makes low voltage information processing possible is a DC-DC converter. These types of converters are widely used to condition power supplied to a circuit from a source such as a battery.
FIG. 1 shows the circuit structure of a conventional charge pump type DC-DC converter 80 formed on a semiconductor chip. The DC-DC converter produces a negative voltage at the output terminal V.sub.OUT. A P-channel MOS transistor M31 and three N-channel MOS transistors M32, M33 and M34 are connected in series between a high-potential power supply V.sub.CC and the output terminal V.sub.OUT. The source of the transistor M31 is connected to the power supply V.sub.CC while its drain is connected to the drain of the transistor M32. The body of the transistor M31 (called "Back Gate") is connected to its own source. The transistor M32 has its source connected to the ground GND as a low-potential power supply, and its body connected to its own source. The transistor M33 has its source connected to the source of the transistor M32, and its drain connected to the source of the transistor M34. The transistor M34 has its drain connected to the output terminal V.sub.OUT and its body connected to its own drain. A first capacitor C11 is provided between the drain of the PMOS transistor M31 and the drain of the NMOS transistor M33. A second capacitor C12 is provided between the output terminal V.sub.OUT and the ground GND.
In the converter 80, when the transistors M31 and M33 are turned on and the transistors M32 and M34 are off, the capacitor C11 is electrically charged by the power supply V.sub.CC. Conversely, when the transistors M31 and M33 are turned off and the transistors M32 and M34 are turned on, the capacitor C11 is discharged. Charge released from the first capacitor C11 is stored into the second capacitor C12. While the transistor pair (M31, M33) and the transistor pair (M32, M34) repeatedly cycle on and off, the converter 80 produces a prescribed voltage V.sub.G (=-V.sub.CC) at the output terminal V.sub.OUT.
N-channel MOS transistors M35 and M36 are connected in series between the source and drain of the transistor M33. The transistor M35 has its drain connected to the source of the transistor M33, and its source connected to the drain of the transistor M36. The source of the transistor M36 is connected to the drain of the transistor M33. The body of the transistor M33 is connected to the source of the transistor M35 and to the drain of the transistor M36.
A toggle flip-flop circuit (hereinafter referred to as TFF) 81 has a clock terminal CK that receives a clock signal CLK whose potential level periodically changes. The TFF 81 has a data terminal D and an inverted output terminal /Q which are connected to each other. The TFF 81 alternately outputs a H-level signal and a L-level signal from an output terminal Q every time it receives pulses of the clock signal CLK. The TFF 81 produces, at the inverted output terminal /Q, a signal whose phase is opposite to that of the output signal at the output terminal Q.
The output terminal Q of the TFF 81 is connected to the gates of the transistors M33 and M35, and to the gate of the transistor M31 via an inverter 82. The inverted output terminal /Q of the TFF 81 is connected to the gates of the transistors M32, M34 and M36. Consequently, all three transistors M31, M33 and M35 turn on or off approximately at the same time in response to the output signal from the output terminal Q. The three transistors M32, M34 and M36 are turned on or off approximately at the same time in response to the output signal from the inverted output terminal /Q. The transistors M32, M34 and M36 turn on and off upon the respective off and on action of the transistors M31, M33 and M35.
In the DC-DC converter 80, as described above, when a H-level signal is output from the output terminal Q and when a L-level signal is output from the inverted output terminal /Q in response to a pulse of the clock signal CLK, the three transistors M31, M33 and M35 turn on and the three transistors M32, M34 and M36 turn off. The first capacitor C11 is connected to the power supply V.sub.CC via the transistor M31, and to the ground GND via the transistor M33. Therefore, as indicated by a chain line, a current flows from the power supply V.sub.CC through the transistor M31, capacitor C11 and transistor T33, to charge the first capacitor C11. As a result, the first lead of the capacitor C11 connected to the transistor M31 reaches the same potential as the power supply V.sub.CC, while the second lead connected to the transistor M33 is set to ground potential (i.e., zero volt).
Since the transistor M35 is turned on in that state, the body of the transistor M33 is grounded. No voltage difference exists between the source and body of the transistor M33, allowing the resistance of the transistor M33, when first turned on, to be fairly small. This results in high-speed charging of the first capacitor C11.
In response to another pulse of the clock signal CLK, the TFF 81 outputs an L-level signal at the output terminal Q and an H-level signal at the inverted output terminal /Q. In response, the three transistors M31, M33 and M35 turn off and the three transistors M32, M34 and M36 turn on. The first lead of the capacitor C11, having the potential of power supply V.sub.CC, is then connected to the ground GND via the transistor M32. The second lead of the capacitor C11, set at ground, is then connected via the transistor M34 to the output terminal V.sub.OUT and to the second lead of the second capacitor C12 on the side of the output terminal V.sub.OUT. Therefore, as indicated by a broken line, a current flows from the second capacitor C12 through the transistor M34, first capacitor C11 and transistor M32. The potential held by the first capacitor C11 is discharged to the second capacitor C12, causing the first lead of the second capacitor C12 to be grounded (i.e., zero volt) and the second lead to reach a potential equal to -V.sub.CC. Since the transistor M34 is turned on, the voltage of -V.sub.CC is applied to the drain of the transistor M33.
When the transistor M36 is on, the body of the transistor M33 being coupled to the drain, is set to the drain potential. This allows the voltage of -V.sub.CC to be applied to the body of the transistor M33. In other words, the body and the drain of the transistor M33 are supplied with the same potential. This prevents a parasitic NPN transistor inherently formed in the transistor M33 from turning on.
FIG. 2 shows a sectional structure of the NMOS transistor M33 that is formed on a semiconductor chip. A P-type semiconductor substrate 84 has an N-type separation layer 85 formed therein. A P-type well (i.e., body or back gate) 86 is formed in the separation layer 85. An N-type drain region 87 and an N-type source region 88 are formed in the P-type well 86 separated by a predetermined interval. The substrate 84 is grounded. A voltage higher than the ground potential is applied to the separation layer 85 by means of a power supply 92. Therefore, when the transistor M33 is off, a reverse bias condition is established between the substrate 84 and the separation layer 85 and between the well 86 and the separation layer 85.
When the transistor M33 is off, a drain voltage V.sub.D of the transistor M33 is reduced by the transistor M34 from zero volt to the output voltage V.sub.G (i.e., -V.sub.CC). At this time, the transistor M36 turns on to reduce a voltage V.sub.BG of the back gate of the transistor M33 to the output voltage V.sub.G. However, since the source of the transistor M36 is connected to the drain of the transistor M33, the drain voltage V.sub.D and the body or channel voltage V.sub.BG change to the output voltage V.sub.G, each with a characteristically different response as shown in FIG. 3. That is, voltages V.sub.O and V.sub.B change to the output voltage V.sub.G such that the body or channel voltage V.sub.BG is always higher than the drain voltage V.sub.D.
If the semiconductor body voltage V.sub.BG and the drain voltage V.sub.D vary with the former being higher than the latter, a parasitic NPN bipolar transistor 89, composed of the separation layer 85 (collector), the P-type well 86 (base) and the drain region 87 (emitter), turns on. This parasitic effect causes a current to flow from the power supply 92 to the output terminal V.sub.OUT via the drain region 87 as the emitter of the bipolar transistor 89. As a result, the NMOS transistor 33 requires increased levels of power to operate.
Moreover, when the parasitic NPN transistor 89 turns on, a current flows through the separation layer 85 to cause a voltage drop at the collector area of the parasitic NPN transistor 89 due to the resistance 91 of the separation layer 85. This effectively turns on a parasitic PNP bipolar transistor 90 composed of the semiconductor substrate 84 (emitter), the separation layer 85 (base) and the P-type well 86 (collector), resulting in latch up and a decrease in conductivity.